Notes on x86 processors

Useful references

Processor core names

CPUID dumps

Intel camp

Intel uses a tick-tock development model. Each tick (2-year) is a shrinking of fabrication process technology and each tock (2-year) is a new microarchitecture.

Family 15, Model 1 = 180 nm Pentium 4/Netburst (Willamette)
Family 15, Model 2 = 130 nm Pentium 4/Netburst (Northwood)
Family 15, Model 3 = 90 nm Pentium 4/Netburst (Prescott)
Family 15, Model 4 = 90 nm Pentium 4/Netburst (Irwindale)
Family 15, Model 6 = 65 nm Pentium 4/Netburst (Cedar Mill)
Family 6, Model 15 (0Fh) = Merom
Family 6, Model 23 (17h) = Penryn
Family 6, Model 26 (1Ah) = 45 nm Core i7 and Xeon (Nehalem)
Family 6, Model 28 (1Ch) = 45 nm Atom (Pineview)
Family 6, Model 30 (1Eh) = 45 nm Core i5/i7 and Xeon (Nehalem)
Family 6, Model 37 (25h) = 32 nm Core i3 (and mobile Core i5/i7) (Clarkdale)
Family 6, Model 42 (2Ah) = 32 nm Core i5/i7 (Sandy Bridge)
Family 6, Model 44 (2Ch) = 32 nm Core i7 and Westmere-EP
Family 6, Model 45 (2Dh) = Sandy Bridge-EP/E5
Family 6, Model 46 (2Eh) = Nehalem-EX
Family 6, Model 47 (2Fh) = Westmere-EX/E7
Family 6, Model 54 (36h) = 32 nm Atom (Cedarview)
Family 6, Model 58 (3Ah) = 22 nm Core i3/i5/i7 (Ivy Bridge)
Family 6, Model 60 (3Ch) = 22 nm Haswell

See this picture (made by Hiroshige Goto) for the Intel x86 CPU evolution.

Microarchitecture Feature size (nm) Desktop Server Features
Sandy Bridge 22 "Ivy Bridge" (IVB) i5 [34/3500-series] (4 cores)
i7 [3700-series] (4 cores)
Sandy Bridge 32 "Sandy Bridge" (SNB) i3 [2100-series] (2 cores)
i5 [23/24/2500-series] (2,4 cores)
i7 [26/27/38/3900-series] (4,6 cores)
Sandy Bridge/E3 [1200-series] (2,4 cores)
Sandy Bridge-EP/E5 ("Jaketown") [16/2600-series] (4,6,8 cores)
AVX
Nehalem 32 "Westmere" Clarkdale:
i3 [500-series] (2 cores)
i5 [600-series] (2 cores)
i7 [900-series] (6 cores)
Westmere-EP/Gulftown [5600-series] (4,6 cores)
Westmere-EX/E7 [2800/4800/8800-series] (6,8,10 cores)
AES instruction set, VMX unrestricted mode
Nehalem 45 "Nehalem" Lynnfield: i5 [700-series], i7 [800-series]
Bloomfield: i7 [900-series]
Nehalem-EP/Gainestown [5500-series] (4 cores)
Nehalem-EX/Beckton [6500/7500-series] (8 cores)

(EP=Efficient Performance, EX=EXpandable)

SSE4.2, QuickPath Interconnect
Core 45 "Penryn" Wolfdale (1,2 cores), Yorkfield (4 cores) Wolfdale (2 cores) [5200-series]
Harpertown [5400-series] (4 cores)
Dunnington [7400-series] (4,6 cores)
SSE4.1 (Penryn New Instructions)
Core 65 "Merom" Conroe (1,2 cores), Allendale (2 cores) Woodcrest [5100-series] (2 cores)
Kentsfield [3200-series]
Clovertown [5300-series]
Tigerton [7200/7300-series] (4 cores)
SSSE3 (Tejas/Merom New Instructions)
NetBurst 65 "Cedar Mill" Pentium D (2 cores) Tulsa [7100-series], Dempsey [5000-series]
NetBurst 90 "Prescott" Pentium 4 Nocona, Irwindale, ... 31 pipeline stages, SSE3 (Prescott New Instructions), Intel 64 EM64T
NetBurst 130 "Northwood" Pentium 4
NetBurst 180 "Willamette" Pentium 4 20 pipeline stages

AMD camp

Family 6 = K7
Family 15 (0Fh) = K8
Family 16 (10h) = K10
Family 17 (11h) = Athlon/Sempron, Athlon/Sempron/Turion X2
Family 18 (12h) = Llano
Family 20 (14h) = Brazos/Bobcat
Family 21 (15h) = Bulldozer

See this picture and this too (both made by Hiroshige Goto) for the AMD x86 CPU evolution.

Microarchitecture Feature size (nm) Desktop Server Features
Piledriver 32 Trinity:
A4 [5300-series] (2 cores)
A6 [5400-series] (2 cores)
A8 [55/5600-series] (4 cores)
A10 [57/5800-series] (4 cores)

Vishera [FX 43/63/8300-series] (4,6,8 cores)

Abu Dhabi [6300-series] (2,4,8,16 cores) F16C, FMA3
Bulldozer 32 Zambezi [FX 41/61/8100-series] (4,6,8 cores) Interlagos [6200-series] (2,4,8,16 cores) XOP, FMA4
K10.5, "Llano" 32 A4 [33/3400-series] (2 cores)
A6 [35/3600-series] (3,4 cores)
A8 [3800-series] (4 cores)
"Fusion" architecture (integrated graphics)
K10, Revision C,D 45 Phenom II (2,3,4,6 cores, 6 MB L3 cache)
Athlon II (2,4 cores, no L3 cache)
Shanghai [2300/8300-series] (Revision C, 4 cores, 6 MB L3 cache)
Istanbul [2400/8400-series] (Revision C, 6 cores, 6 MB L3 cache)
Magny-Cours [6100-series] (Revision D, 8,12 cores, 2x6 MB L3 cache)
Lisbon [4100-series] (Revision D, 4,6 cores, 6 MB L3 cache, HyperTransport 3.1)
K10 "Barcelona" 65 Phenom (3,4 cores, 2 MB L3 cache) Barcelona [2300/8300-series]
Budapest [1300-series] (4 cores, 2 MB L3 cache)

Barcelona and Budapest mark the beginning of the third-generation Opterons.

SSE4a (Phenom New Instructions)
K8, Revision G 65 Sempron, Athlon 64 X2
K8, Revision D,E,F 90 Athlon 64, Athlon 64 X2, Sempron Venus, Troy, Athens (1 core), Denmark, Italy, Egypt (2 cores)

Santa Ana [1200-series], Santa Rosa [2200/8200-series] (2 cores)

Santa Ana and Santa Rosa are second-generation Opterons.

SSE3
K8, "Athlon 64" 130 Athlon 64, Sempron Sledgehammer (1 core) x86-64
K7 130 Athlon (Thoroughbred, Barton, Thorton)

AMD Athlon chronology

Codename Features Release
Athlon (K7) Argon June 1999
Athlon XP (K7) Palomino
There is also Athlon MP for dual processing.
3DNow! Professional, SSE October 2001
Athlon XP (K7) Thoroughbred A/B June 2002
Athlon 64 (K8) Clawhammer/Newcastle x86-64, NX, Cool'n'Quiet April 2004
Athlon 64 (K8) Winchester 90 nm fabrication October 2004
Athlon 64 X2 (K8) Toledo Dual core May 2005
Athlon 64 X2 (K8) Brisbane 65 nm fabrication December 2006
Phenom X4 (K10) Agena SSE4a, quad-core, L3 cache November 2007
Phenom X3 (K10) Toliman Triple-core March 2008
Athlon X2 (K10) Kuma December 2008
Phenom II X4 (K10) Deneb 45 nm fabrication, 6 MB L3 cache January 2009
Athlon II X2 (K10) Regor June 2009
Athlon II X3 (K10) Rana October 2009
Athlon II X4 (K10) Propos September 2009
Phenom II X6 (K10) Thuban Hexa-core April 2010
Phenom II X4 (K10) Zosma June 2010