Useful references
ARM Cortex-A seriesBrawny cores still beat wimpy cores, most of the time by Urs Holzle of Google
ARM versus x86 performance comparison
12-core ARM cluster benchmarked against Intel Atom, Ivy Bridge, AMD Fusion
ARM Cortex-A family architecture by Hiroshige Goto
ARM Cortex-A series
| Architecture | Instruction set | Extra features | Clock rate (GHz) | Cores | Implementations |
|---|---|---|---|---|---|
| Cortex-A5 | ARM v7, Jazelle, Thumb-2 | DSP, VFPv3 floating point (optional), NEON SIMD (optional) In-order, 9-stage single-decode pipeline |
0.53-1 | 1-4 | |
| Cortex-A7 | ARM v7, Jazelle, Thumb-2 | DSP, VFPv4 floating point, NEON SIMD, virtualization In-order, 8-stage limited dual-decode pipeline |
> 1 | 1-4 | |
| Cortex-A8 | ARM v7, Thumb-2 | VFPv3 floating point, NEON SIMD | 0.53-1 | 1 | Apple A4, Freescale I.MX5?, Samsung Hummingbird, TI OMAP3 In-order, 13-stage dual-decode pipeline |
| Cortex-A9 | ARM v7, Jazelle, Thumb-2 | DSP, VFPv3 floating point (optional), NEON SIMD (optional) | 0.8-2 | 1-4 | Apple A5/A6, nVidia Tegra 2, Samsung Exynos 4210, ST-Ericsson NovaThor U8500, TI OMAP4 Out-of-order, 9-12 stage dual-decode pipeline |
| Cortex-A15 | ARM v7, Jazelle, Thumb-2 | TrustZone, VFPv4 floating point, 40-bit Large Physical Address Extensions, Virtualization, L2 cache Out-of-order, 15+ stages triple-decode pipeline |
1-2.5 | 1-32 | ST-Ericsson Nova A9600, TI OMAP5, Samsung Exynos5 |
